1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to chemical mechanical polishing (CMP) using dual slurry particle sizes for reducing microscratching of wafers.
2. Description of the Related Art
CMP is a widely used means of planarizing silicon dioxide as well as other types of processing layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, a surface of a process layer formed above the wafer is mechanically and chemically polished.
As semiconductor devices are scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to minimize surface damage, such as microscratching, to either a post-polish surface of a process layer or the wafer. For example, in one embodiment, during a CMP process, abrasive particles within the slurry may be used to mechanically abrade a polishing surface of a process layer that has been formed above the wafer. As the wafer is polished, the interaction between the polishing surface and the abrasive particles may produce undesirable surface damage (e.g., microscratches) to the post-polish surface of the process layer.
In one illustrative embodiment, an oxide layer of a wafer may be planarized using a conventional CMP process (i.e., the surface of the oxide layer may be polished to produce a more uniform layer of material.) During this process, the interaction between the abrasive particles within the slurry and the surface of the oxide layer may produce small undesirable microscratches in the polished surface of the oxide layer. For example, depending upon the processing parameters of the polishing process (e.g., polishing time, slurry composition, carrier arm down force, etc.), the polishing process may produce microscratches in the polished surface of the oxide layer that are several microns long and have a depth of approximately 0.5 .mu.m. If not removed, the microscratches may "trap" portions of additional processing layers within the oxide layer during subsequent processing steps.
For example, once the polishing of the oxide layer is complete, depending upon the particular process, additional process layers may be formed on the polished surface of the oxide layer. With one exemplary process, a conductive layer of material, such as metal, may be deposited on the polished surface of the oxide layer. As with conventional processing, the metal processing layer may be patterned, etched, and/or polished to produce at least a portion of a desired integrated circuit feature or configuration. For example, a blanket metal layer comprised of tungsten or copper may be formed above openings in the oxide layer and then subsequently polished to form electrical paths (e.g., interconnects) between stacked processing layers. Unfortunately, if microscratches are present in the polished surface of the oxide layer, portions of the metal processing layer may become "trapped" within the oxide layer, which may result in poor performance of the finished semiconductor device. For example, the "trapped" portion of the metal layer may produce a short circuit condition within the finished device or, in a less extreme case, undesirably high electrical leakage between adjacent metal lines.
One conventional method for alleviating polishing induced damage to the surface of a wafer or a processing layer is post-polish buffing. For example, once the CMP process is complete, the polishing surface of the wafer or the processing layer may be processed through a "buff" step, which may at least partially reduce the severity of any surface damage. In one embodiment, the "buff" step comprises positioning the polished surface of a process layer against a rotating buffing pad that has been mounted to a secondary platen. The wafer may then be rotated and pressed against the buffing pad for a predetermined amount of time.
The existing methods for alleviating surface damage present on the post-polish surface of a wafer or processing layer, however, suffer from several shortcomings. For example, with existing techniques, significant surface damage, such as deep microscratches, may not be completely removed. When this occurs, depending upon the application, the residual damage remaining on the polishing surface of the wafer or the processing layer may contribute to impaired final device performance. Additionally, conventional methods for alleviating polishing induced surface damage may decrease wafer throughput, thus, increasing the cost of the manufacturing process.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.